Conventional charge-coupled device (CCD) line imagers use two readout shift registers. The maximum pixel density of this bilinear design is limited by the minimum polysilicon overlap and spacing design rules in the shift registers. Pixel density can be increased by employing a quadrilinear shift register organization to relieve these design rule constraints. See, for example application Ser. No. 285,250, which is assigned to the same assignee as the present invention. Further, reference is made to an article by H. Herbst and H. J. Peleiderer, "Modulation Transfer Function of Quadrilinear CCD Imager", Electronics Letters, Volume 12, Number 25, pps. 676 and 677, 1976. However, as the imager resolution and pixel density increase even further, a new limitation arises due to the narrowing of the CCD parallel transfer channels. That is, the channel between the inner shift register and the outer shift register, in such a quadrilinear register array, becomes narrower due to the increased density of circuitry on a fixed length integrated circuit chip. This narrowing of the charge transfer path from the inner to the outer shift register decreases the minimum potential of the channel which therefore affects the charge transfer efficiency from the inner to the outer shift register. In order to accomplish higher density charge coupled device imagers, this potential barrier problem must be overcome.
According to the present invention, a high resolution element quadrilinear CCD imager array is utilized with a novel structure to eliminate the narrow channel effect which decreases the parallel charge transfer efficiency. In such a charge coupled device imager, the barrier gate material is utilized to define the channel rather than the field oxide as set forth in the prior art. In addition, the storage gate is made wider and overlaps the field oxide as a further element in defining the principles of the present invention.